Research Inventy: International Journal of Engineering And Science
Vol.4, Issue 2 (February 2014), PP -56-59
Issn (e): 2278-4721, Issn (p):2319-6483, www.researchinventy.com
Novel Advanced Method for the Square and Cube Architectures
Using Vedic Sutras
T. Maheshwar1, A Rama1, A Sereesha1,
ECE Department, Sree Dattha Institute of Engineering & Science
Abstract: Square and cube architectures can be uses as element in such applications like DSP, DIP, and
communication and etc .there is different ways for designing this circuit as if with the multiplier. That is not the
ideal approach of designing in present advanced systems with the power, speed and area. We proposes a novel
approach of designing the square and cube architectures by using the one of the fast and less power method
called Anurupyena sutra of Vedic mathematics. These are very efficient because the operation not as with the
normal, and also the have the pipelined execution feature. In proposed design Vedic multiplication method
Urdhwa Tiryakbhyam Sutra is chosen for the sub module design. There by decreases the critical path delay
compare to that of any other alternative method. The designing can done using verilog and simulated using
model-sim and synthesized using Xilinx
Keywords: Square,Cube, Anurupyena, Urdhwa Tiryakbhyam Sutra, Vedic Mathematics
As expanding the application of the present modern systems high speed architecture are necessitate in
demand. These arithmetic operations needs higher throughput ids desired for the real time processing
applications like image processing (compression and decompression), image encoding and decoding,
communications, adaptive networking, least means square and data encryption and decryption requires square
and cube architectures.
They also requires the time delay and power consumption is more essential Up till now the square and
cube systems are designed using normal methods composes of multiplier. Normally the multiplier is more
power consumed digital design as this internally consists the partial product generation and multi operand
addition and final addition that causes the increases the area and power in advancement of present VLSI features
we cannot accept this type of designing .
Even in for the design of performance increased multiplier the present researches are moving to vedic
mathematic approaches. vedic mathematic is one of the promising alternative for the present ALU requirements.
In this work we have put into effect a high speed and less power square and cube architectures. The
architectures implemented by Anurupyena sutra due to its feature fat operation and multiplier less architecture.
The Urdhwa Tiryakbhyam Sutra used at different levels of design drastically reduces the delay when compared
to conventional designs. The hardware implementation of square and cube Vedic designs using Anurupyena
sutra contributes to adequate improvement of the speed in order to achieve high outturn.
Section II provides a related introduction towards Vedic sutras. Section III describes the proposed architecture.
Section IV simulation results and design analysis of square and cube architectures and proposed design. Section
V represents the conclusions. Followed by references
II. Vedic Mathematics
Vedic math is taken from the traditional Indian Vedas; they are very much used in India for fast oral
calculation without paper and pen. The technique in that the calculation are carried out by using the different
main 16 sutras, different upa sutras and inferences derived from these Sutras. Algebra, arithmetic, geometry or
trigonometry etc any mathematical calculation can be carried out by this sutra efficiently. Vedic Mathematics is
more tenacious than modern mathematics.
Generally the “Vedic mathematics” is comprised of sixteen simple mathematical formulae from the Vedas .
1. Ekadhikena Purvena
2. Nikhilam navatascaramam Dasatah
3. Urdhva - tiryagbhyam
4. Paravartya Yojayet
5. Sunyam Samya Samuccaye
6. Anurupye - Sunyamanyat
7. Sankalana - Vyavakalanabhyam
9. Calana - Kalanabhyam
Novel Advanced Method for the Square and Cube Architectures Using Vedic Sutras
Fig 5: cube design output
Vedic square and cube multiplier can be designed with the advanced design methods can be done that
makes the efficient design and reduces the operation time. The extra advanced logic MCM based design can be
done. Rather than using the normal multiplier MCM can uses the very less area. We designed the 8-bit, 16-bit
and 32- bit architectures are designed and comparison evaluation can be carried out in this paper.
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