MOS Transistor Theory

This set of MCQs helps students to learn about MOS transistor theory which is a majority-carrier device, in which the current in a conducting channel between the source and the drain is modulated by a voltage applied to the gate.

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The conductivity of the pure silicon is raised by:

Introducing Dopants (impurities) Increasing Pressure Decreasing Temperature Deformation of Lattice

The n-type semiconductor have _______ as majority carriers.

Holes Negative ions Electrons Positive ions

The majority carriers of p-type semiconductor are:

Holes Negative ions Electrons Positive ions

The n-MOS transistor is made up of:

N-type source, n-type drain and p-type bulk N-type source, p-type drain and p-type bulk P-type source, n-type drain and n-type bulk P- type source, p-type drain and n-type bulk

The oxide layer formed in the MOSFET is:

Metal oxide Silicon dioxide Poly Silicon oxide Oxides of Non metals

The drain current is varied by:

Gate to source voltage Gate current Source Voltage None of the mentioned

The low voltage on the gate of p-MOSFET forms:

Channel of negative carriers Channel is not formed Channel is clipped Channel of positive carriers

The n-MOSFET is working as accumulation mode when:

Gate is applied with positive voltage Gate is grounded Gate is applied with negative voltage Gate is connected to source

The n-MOS invertor is better than BJT in terms of:

Fast switching time Low power loss Smaller overall layout area All the mentioned

If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:

Source of both transistor Drains of both transistor Drain of n-MOS and source of p-MOS Source of n-MOS and drain of p-MOS

What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS inverter circuit are exchanged?

Output is same Output is reversed Output is always high Output is always low

The average power dissipated in resistive load n-MOS inverter is:

0 VDD (VDD-VOL)/R VDD (VDD-VOL)/2R VDD (VDD-VIH)/2R

The enhancement mode n-MOS load inverter requires 2 different supply voltages to:

Keep load transistor in cutoff region Keep load transistor in linear region Keep load transistor in saturation region None of the mentioned

The CMOS inverter consists of:

Enhancement mode n-MOS transistor and depletion mode p-MOS transistor Enhancement mode p-MOS transistor and depletion mode n-MOS transistor Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor

In the CMOS inverter the output voltage is measured across:

Drain of n-MOS transistor and ground Source of p-MOS transistor and ground Source of n-MOS transistor and source of p-MOS transistor Gate of p-MOS transistor and Gate of n-MOS transistor

Quiz/Test Summary

Title: MOS Transistor Theory

Questions: 15

Contributed by:

Steve Wed, Apr 06, 2022 08:27 AM UTC

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