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This set of MCQs helps students to learn about memory, registers and aspects of system timing, which is used to handle the address transferred to the memory unit, and this can be handled either using a bus approach (which we have used in this architecture) or direct input declaration for the memory.
Which occupies lesser area?
In which design, dissipation is less?
Which implementation is slower?
A bit is read at T1 when
Which clock is preferred in storage devices?
Single phase overlapping clock signal
Single phase non overlapping clock signal
Two phase overlapping clock signal
Two phase non overlapping clock signal
Clock signal Φ2 is to :
Write data
Read data
Refresh data
Store data
The impedance of pull down transistor in nMOS can be given as,
2Rs
4Rs
1/2 Rs
1/4 Rs
Factor for assessment of storage elements are,
Volatility
Non volatility
Number of bits
Data repeatability
Data storage time is,
1 milli second
1 second
1 minute
10 seconds
Data storage time is,
1 milli second
1 second
1 minute
10 seconds
Static RAM uses ____________ transistors.
Four
Five
Six
Seven
Which cell is non volatile?
One transistor dynamic cell
Two transistor dymanic cell
Four transistor dynamic cell
Pseudo static RAM cell
RAM is a _____ cell.
Dynamic
Partially dynamic
Static
Pseudo static
Reading a cell is a _______ operation.
Constructive
Destructive
Semi constructive
Semi destructive
Data is read,
Before Φ1
After Φ1
Before Φ2
After Φ2
A bit can be stored when,
RD is low, WR is low
RD is high, WR is low
RD is low, WR is high
RD is high, WR is high
