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This set of MCQs helps students to learn about Pentium 4 processor, which was a series of single-core central processing units (CPU) for desktop PCs and laptops. The series was designed by Intel and launched in November 2000. Pentium 4 clock speeds were over 2.0 GHz and also replaced the Pentium III via an embedded seventh-generation x86 microarchitecture, known as Net burst Microarchitecture, which was the first new chip architecture launched after the P6 microarchitecture in the 1995 Pentium Pro CPU model.
For single precision floating point numbers, the SSE instructions are
The new instructions that are added in SSE for floating point operations are of
The feature of Pentium 4 is :
Works based on Net Burst microarchitecture
Clock speed ranges from 1.4GHz to 1.7GHz
Has hyper-pipelined technology
All of the mentioned
Which of the following is not a module of Pentium 4 architecture?
Front end module
Execution module
Control module
None
The front module of Pentium 4 consists of :
Trace cache
Microcode ROM
Front end branch predictor
All of the mentioned
The unit that decodes the instructions concurrently and translate them into micro-operations is,
Trace cache
Instruction decoder
Execution module
Front end branch predictor
In complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to :
Trace cache
Front end branch predictor
Microcode ROM
None
The unit that does not store the instructions, but the decoded stream of instructions is
Trace cache
Front end branch predictor
Microcode ROM
None
Trace cache can store the micro-ops upto a range of :
6 K decoded micro-ops
8 K decoded micro-ops
10 K decoded micro-ops
12 K decoded micro-ops
The unit that predicts the locations from where the next instruction bytes are fetched is,
Trace cache
Front end branch predictor
Execution module
Instruction decoder
The unit that predicts the locations from where the next instruction bytes are fetched is,
Trace cache
Front end branch predictor
Execution module
Instruction decoder
If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
Microcode ROM
Front end branch predictor
Execution module
Instruction decoder
After the micro-ops are issued by the microcode ROM, the control goes to
Trace cache
Front end branch predictor
Execution module
Instruction decoder
The feature of SSE among the following is,
Operate on four 32-bit floating points
Register size is of 128 bits
No switching from one mode to other
All of the mentioned
The SSE instructions can operate on :
Packed data
Unpacked data
Dynamic data
All of the mentioned
Which of the following group is not of SSE instructions?
jump or branch group of instruction
logic and comparison group of instruction
Shuffle instructions
All of the mentioned
