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This set of MCQs helps students to learn about recent advancements in microprocessor architecture, some of the recent advancements in designing of the microprocessors. The technology that permits ARM processors that implement it, to run Java bytecode and is often used by mobile phone manufacturers to speed up the execution of Java games and apps, which is probably what drove the development of the technology.
The number of stages of the integer pipeline, U, of Pentium is
In the data type, packed byte, the number of bytes that can be packed into one 64-bit quantity is
The salient feature of Pentium is,
Superscalar architecture
Superpipelined architecture
Superscalar and superpipelined architecture
None of the mentioned
Which of the following is a cache of Pentium?
Data cache
Data cache and instruction cache
Instruction cache
None of the mentioned
The speed of integer arithmetic of Pentium is increased to a large extent by,
On-chip floating point unit
Superscalar architecture
4-stage pipelines
All of the mentioned
For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of:
Super pipelined technique
Multiple instruction issue
Super pipelined technique and multiple instruction issue
None of the mentioned
Which of the following is a class of architecture of MII (multiple instruction issue)?
Super pipelined architecture
Multiple instruction issue
Very small instruction word architecture
Super scalar architecture
The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in :
Super pipelined architecture
Multiple instruction issue
Very long instruction word architecture
Super scalar architecture
The architecture in which the hardware decides which instructions are to be issued concurrently at run time is,
Super pipelined architecture
Multiple instruction issue
Very long instruction word architecture
Superscalar architecture
Four words can be packed into 64-bit by using the data type,
Unpacked word
Packed word
Packed doubled word
One quad word
The number of double words that can be packed into 64-bit register using packed double word is,
2
4
6
8
The data type, “one quad word” packs __________ into 64-bit.
Two 32-bit quantities
Four 16-bit words
One 32-bit and two 16-bit quantities
One single 64-bit quantity
If the result of an operation is overflowed(exceeded than 16 bits) or underflowed then, only the lower 16-bits of the result are stored in the register and this effect is known as,
Overflow/underflow effect
Wrap-around effect
Exceeding memory effect
None
