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This set of MCQs helps students to learn about DMA, floppy disk and CRT controllers whose mode of data transfer is the fastest amongst all the modes of data transfer and its functions is to store the address of the starting memory location, which will be accessed by the DMA channel.
To indicate the I/O device that its request for the DMA transfer has been honored by the CPU, the DMA controller pulls
In direct memory access mode, the data transfer takes place
Directly
Indirectly
Directly and indirectly
None of the mentioned
The common register(s) for all the four channels of 8257 is,
DMA address register
Terminal count register
Mode set register and status register
None of the mentioned
In 8257 register format, the selected channel is disabled after the terminal count condition is reached when,
Auto load is set
Auto load is reset
TC STOP bit is reset
TC STOP bit is set
In 8257 (DMA), each of the four channels has
A pair of two 8-bit registers
A pair of two 16-bit registers
One 16-bit register
One 8-bit register
The IOR (active low) input line acts as output in,
Slave mode
Master mode
Master and slave mode
None of the mentioned
The IOW (active low) in its slave mode loads the contents of a data bus to,
8-bit mode register
Upper/lower byte of 16-bit DMA address register
Terminal count register
All of the mentioned
The pin that disables all the DMA channels by clearing the mode registers is,
MARK
CLEAR
RESET
READY
The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is,
AEN
ADSTB
TC
None of the mentioned
The pin that requests the access of the system bus is,
HLDA
HRQ
ADSTB
None of the mentioned
The pin that is used to write data to the addressed memory location, during DMA write operation is
MEMR (active low)
AEN
MEMW (active low)
IOW (active low)
The 8257 is able to accomplish the operation of,
Verifying DMA operation
Write operation
Read operation
All of the mentioned
The bus is available when the DMA controller receives the signal,
HRQ
HLDA
DACK
All of the mentioned
The number of clock cycles required for an 8257 to complete a transfer is,
2
4
8
None of the mentioned
The continuous transfer may be interrupted by an external device by pulling down the signal.
HRQ
DACK (active low)
DACK (active high)
HLDA
