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This set of MCQs helps students to learn about scaling of MOS circuits which is concerned with reducing the dimension of the device. The size of a MOS transistor is reduced by a factor of 0.7 in each technology generation . Scaling results in the decrease of the dimensions of a MOS device, and thus increases the device density and functional capacity of the chip.
For constant voltage model,
For constant electric field model,
Built-in junction potential Vb depends on,
Vdd
Vgs
Substrate doping level
Oxide thickness
As the channel length is reduced in a MOS transistor, depletion region width must be
Increased
Decreased
Must not vary
Exponentially decreased
Vdd is scaled by,
α
β
1/α
1/β
Maximum electric field can be given as,
V/d
d/V
2V/d
d/2V
If doping level of substrate Nb increases then depletion width,
Increases
Decreases
Does not change
Increases and then decreases
Microelectronic technology cannot be characterized by,
Minimum feature size
Power dissipation
Production cost
Designing cost
Which model is used for scaling?
Constant electric scaling
Constant voltage scaling
Constant electric and voltage scaling
Constant current model
Gate area can be given as,
L/W
L * W
2L/W
L/2W
Gate area is scaled by,
α
1/α
1/α2
α2
α is used for scaling :
linear dimensions
Vdd
Oxide thickness
Non linear
Gate capacitance per unit area is scaled by,
α
1
1/β
β
Parasitic capacitance is scaled by,
β
1/β
α
1/α
