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This set of MCQs helps students to learn about multimicroprocessors Systems, which are being used successfully today to improve performance in systems running multiple programs concurrently. In addition, multiprocessor systems have shown the ability to improve single-program performance significantly for certain applications containing easily parallelized loops. The extraction of coarse-grained prallelism from a software description and, indeed, the study of languages used to describe parallel software are a flourishing area of research.
Which of the following is not a general purpose register of 8089?
In multiport memory configuration, the processor(s) that address the multiport memory is(are)
1
2
3
Many
Bus switches are present in,
Bus window technique
Crossbar switching
Linked input/output
Shared bus
The memory space of a processor that is mapped to other processor/processors and vice-versa is known as,
Multi microprocessor system
Memory technique
Bus window technique
Mapping technique
The memory of a microprocessor serves as,
Storage of individual instructions
Temporary storage for the data
Storing common instructions or data for all processors
All of the mentioned
In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is:
One processor
Two processors
More than two processors
None of the mentioned
The disadvantage of the bus window technique is,
Both processors must know about bus window
Both processors must know the address map
Loss of effective local memory space
All of the mentioned
Which of the following is not a type of configuration that is based on physical interconnections between the processors?
Star configuration
Loop configuration
Regular topologies
Incomplete interconnection
The configuration, in which all the processing elements are connected to a central switching element, that may be independent processor via dedicated paths is,
Star
Loop
Complete
Irregular
The configuration that is not suitable for a large number of processors is,
Star
Loop
Complete
Regular
The array processor architecture is an example of,
Star
Loop
Complete
Regular
The registers that are used as source and destination pointers during DMA operations are,
GB, GC
GC, BC
GC, GA
GA, GB
In the 8089 architecture, the address of memory table for channel-2 is calculated by,
Adding 16 to the contents of CCP
Adding 8 to the contents of CCP
Adding memory table address of channel-1
None of the mentioned
The pin that is used to inform the CPU that the previous operation is completed is,
RQ (active low)
GT (active low)
DRQ
SINTR
The pin that is used for data transfer control and operation termination signals is,
SINTR
EXT
DRQ and EXT
RQ (active low) or GT (active low)
