Embedded Processors

This is an MCQ-based quiz on Embedded Processors.

This includes Databus, Barrel Shifter, Incrementer, and Instruction Decoder.

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In Intel x86 architecture, which general purpose register is used for repeated string instructions as well as shift, rotate and loop instructions?

EAX (Accumulator) ECX (Counter) EDX (Data register) EBP (Data Pointer)

Which status flag in x86 family is used to enable or disable the interrupt especially when the Pentium processor operates in the virtual mode?

ID VIP VIF AC

Which control register in x86 family is reserved for future use and generally not adopted for current implementation?

CR0 CR1 CR2 CR4

Which functional unit of ARM family architecture is responsible for upgrading the address register contents before the core reads or writes the next register value from memory location?

Data bus Barrel Shifter Incrementer Instruction Decoder

Which type of non-privileged processor mode is entered due to raising of high priority of an interrupt?

User mode Fast Interrupt Mode (FIQ) Interrupt Mode (IRQ) Supervisor Mode (SVC)

In DAC 0808, what is the high speed multiplying input slew rate?

2 mA/μ sec 4 mA/μ sec 8 mA/μ sec 16 mA/μ sec

In DAC 0808, which among the following is configured as a reference in addition to R-2R ladder and current switches?

Voltage amplifier Current amplifier Transconductance amplifier Transresistance amplifier

What is/are the configuration status of control unit in RISC Processors?

Hardwired Microprogrammed Both a and b None of the above

While designing an embedded system, which sub-task oriented process allocates the time steps for various modules that share the similar resources?

Simulation and Validation Iteration Hardware-Software Partitioning Scheduling

Which mode of operation is exhibited by RS-485 standard?

Single ended Differential Both a and b None of the above

In CPU structure, which register provides the address for fetching of data or instruction especially by means of processor?

Data Register Instruction Register Accumulator Memory Address Register

In ADSP 21xx architecture, which notation represents ALU overflow condition?

AC AV NE EQ

Which kind of low-order 16 bits control register is also regarded as ‘Machine Status Word’ (MSW) in order to make it compatible with i286?

CR0 CR1 CR2 CR3

In the test registers, what do/does the linear address bit hold/s with respect to TLB (Translation Look-aside Buffers)?

Physical address Selection between write and lookup of TLB Tag field All of the above

Which provides an input clock for the receiver part of the UART 8250?

DDIS MR RD RCLK

What is approximate data access time of SRAM?

2ns 10ns 60ns 4ns

Which of the following is not a characteristic of a virus?

Virus destroy and modify user data Virus is a standalone program Virus is a code embedded in a legitimate program Virus cannot be detected

At an active HIGH reset pin of 8051 microcontroller, for how many machine cycles should the positive going pulse be provided, if the power is switched ON?

Only one

Two

Three

Four

Which of the following is the biggest challenge in the cache memory design?

Coherency

Memory access

Size

Delay

What does PCM stand for?

Peculiar code modulation

Pulse codec machine